Company Description It all started when engineer Fred Luddy wrote code that automated a tedious task for his coworker, Phyllis. She cried tears of joy. That moment inspired Fred to build a company that could do that for everyone—freeing people from busywork so they could focus on meaningful work. Today, ServiceNow is the AI control tower for business reinvention. Our ServiceNow AI platform brings together any AI, any data, and any workflow— helping 85% of the Fortune 500® work smarter, faster, and better. We're building an AI-native culture where technology and talent are unstoppable together. And we're just getting started. Join us to put AI to work for people. Job Description What you get to do in this role: You will design, build, and operate components of our Kubernetes platform and its core subsystems, owning a well-scoped area end to end. You will write and review a lot of Go—controllers, operators, platform services, and the automation around them. You will take a defined problem with open design questions and drive it to a working, production-ready answer, checking in on direction rather than needing it handed to you. You will help operate what the team builds: on-call, incident investigation, and the follow-up work that stops the same failure twice. You will contribute to how workloads run on the platform, working with the teams that depend on it. You will work on a platform that serves regulated markets, where compliance constraints including Fed
Sep 04, 2026
Full time
Company Description It all started when engineer Fred Luddy wrote code that automated a tedious task for his coworker, Phyllis. She cried tears of joy. That moment inspired Fred to build a company that could do that for everyone—freeing people from busywork so they could focus on meaningful work. Today, ServiceNow is the AI control tower for business reinvention. Our ServiceNow AI platform brings together any AI, any data, and any workflow— helping 85% of the Fortune 500® work smarter, faster, and better. We're building an AI-native culture where technology and talent are unstoppable together. And we're just getting started. Join us to put AI to work for people. Job Description What you get to do in this role: You will design, build, and operate components of our Kubernetes platform and its core subsystems, owning a well-scoped area end to end. You will write and review a lot of Go—controllers, operators, platform services, and the automation around them. You will take a defined problem with open design questions and drive it to a working, production-ready answer, checking in on direction rather than needing it handed to you. You will help operate what the team builds: on-call, incident investigation, and the follow-up work that stops the same failure twice. You will contribute to how workloads run on the platform, working with the teams that depend on it. You will work on a platform that serves regulated markets, where compliance constraints including Fed
Company Description It all started when engineer Fred Luddy wrote code that automated a tedious task for his coworker, Phyllis. She cried tears of joy. That moment inspired Fred to build a company that could do that for everyone—freeing people from busywork so they could focus on meaningful work. Today, ServiceNow is the AI control tower for business reinvention. Our ServiceNow AI platform brings together any AI, any data, and any workflow— helping 85% of the Fortune 500® work smarter, faster, and better. We're building an AI-native culture where technology and talent are unstoppable together. And we're just getting started. Join us to put AI to work for people. Job Description What you get to do in this role: You will design, build, and operate components of our Kubernetes platform and its core subsystems, owning a well-scoped area end to end. You will write and review a lot of Go—controllers, operators, platform services, and the automation around them. You will take a defined problem with open design questions and drive it to a working, production-ready answer, checking in on direction rather than needing it handed to you. You will help operate what the team builds: on-call, incident investigation, and the follow-up work that stops the same failure twice. You will contribute to how workloads run on the platform, working with the teams that depend on it. You will work on a platform that serves regulated markets, where compliance constraints including Fed
Sep 04, 2026
Full time
Company Description It all started when engineer Fred Luddy wrote code that automated a tedious task for his coworker, Phyllis. She cried tears of joy. That moment inspired Fred to build a company that could do that for everyone—freeing people from busywork so they could focus on meaningful work. Today, ServiceNow is the AI control tower for business reinvention. Our ServiceNow AI platform brings together any AI, any data, and any workflow— helping 85% of the Fortune 500® work smarter, faster, and better. We're building an AI-native culture where technology and talent are unstoppable together. And we're just getting started. Join us to put AI to work for people. Job Description What you get to do in this role: You will design, build, and operate components of our Kubernetes platform and its core subsystems, owning a well-scoped area end to end. You will write and review a lot of Go—controllers, operators, platform services, and the automation around them. You will take a defined problem with open design questions and drive it to a working, production-ready answer, checking in on direction rather than needing it handed to you. You will help operate what the team builds: on-call, incident investigation, and the follow-up work that stops the same failure twice. You will contribute to how workloads run on the platform, working with the teams that depend on it. You will work on a platform that serves regulated markets, where compliance constraints including Fed
Company Description It all started when engineer Fred Luddy wrote code that automated a tedious task for his coworker, Phyllis. She cried tears of joy. That moment inspired Fred to build a company that could do that for everyone—freeing people from busywork so they could focus on meaningful work. Today, ServiceNow is the AI control tower for business reinvention. Our ServiceNow AI platform brings together any AI, any data, and any workflow— helping 85% of the Fortune 500® work smarter, faster, and better. We're building an AI-native culture where technology and talent are unstoppable together. And we're just getting started. Join us to put AI to work for people. Job Description We're looking for a Staff Full Stack Developer to help build and scale our AI-powered tools for application development. You'll work at the intersection of UI, backend, and AI-driven engineering — architecting solutions that improve developer experience, expand platform capabilities, and drive engineering excellence across the team. What you'll do: Design and implement AI-powered tools for application development, using cutting-edge technical approaches to deliver business value Architect and build core web technology stacks — authentication, event tracking, application platform, and design systems Drive architecture and engineering standards at the team and division level, promoting best practices for building modular, scalable web apps and APIs Design, develop, and maintain micro
Sep 02, 2026
Full time
Company Description It all started when engineer Fred Luddy wrote code that automated a tedious task for his coworker, Phyllis. She cried tears of joy. That moment inspired Fred to build a company that could do that for everyone—freeing people from busywork so they could focus on meaningful work. Today, ServiceNow is the AI control tower for business reinvention. Our ServiceNow AI platform brings together any AI, any data, and any workflow— helping 85% of the Fortune 500® work smarter, faster, and better. We're building an AI-native culture where technology and talent are unstoppable together. And we're just getting started. Join us to put AI to work for people. Job Description We're looking for a Staff Full Stack Developer to help build and scale our AI-powered tools for application development. You'll work at the intersection of UI, backend, and AI-driven engineering — architecting solutions that improve developer experience, expand platform capabilities, and drive engineering excellence across the team. What you'll do: Design and implement AI-powered tools for application development, using cutting-edge technical approaches to deliver business value Architect and build core web technology stacks — authentication, event tracking, application platform, and design systems Drive architecture and engineering standards at the team and division level, promoting best practices for building modular, scalable web apps and APIs Design, develop, and maintain micro
Company Description It all started when engineer Fred Luddy wrote code that automated a tedious task for his coworker, Phyllis. She cried tears of joy. That moment inspired Fred to build a company that could do that for everyone—freeing people from busywork so they could focus on meaningful work. Today, ServiceNow is the AI control tower for business reinvention. Our ServiceNow AI platform brings together any AI, any data, and any workflow— helping 85% of the Fortune 500® work smarter, faster, and better. We're building an AI-native culture where technology and talent are unstoppable together. And we're just getting started. Join us to put AI to work for people. Job Description We're looking for a Staff Full Stack Developer to help build and scale our AI-powered tools for application development. You'll work at the intersection of UI, backend, and AI-driven engineering — architecting solutions that improve developer experience, expand platform capabilities, and drive engineering excellence across the team. What you'll do: Design and implement AI-powered tools for application development, using cutting-edge technical approaches to deliver business value Architect and build core web technology stacks — authentication, event tracking, application platform, and design systems Drive architecture and engineering standards at the team and division level, promoting best practices for building modular, scalable web apps and APIs Design, develop, and maintain micro
Sep 02, 2026
Full time
Company Description It all started when engineer Fred Luddy wrote code that automated a tedious task for his coworker, Phyllis. She cried tears of joy. That moment inspired Fred to build a company that could do that for everyone—freeing people from busywork so they could focus on meaningful work. Today, ServiceNow is the AI control tower for business reinvention. Our ServiceNow AI platform brings together any AI, any data, and any workflow— helping 85% of the Fortune 500® work smarter, faster, and better. We're building an AI-native culture where technology and talent are unstoppable together. And we're just getting started. Join us to put AI to work for people. Job Description We're looking for a Staff Full Stack Developer to help build and scale our AI-powered tools for application development. You'll work at the intersection of UI, backend, and AI-driven engineering — architecting solutions that improve developer experience, expand platform capabilities, and drive engineering excellence across the team. What you'll do: Design and implement AI-powered tools for application development, using cutting-edge technical approaches to deliver business value Architect and build core web technology stacks — authentication, event tracking, application platform, and design systems Drive architecture and engineering standards at the team and division level, promoting best practices for building modular, scalable web apps and APIs Design, develop, and maintain micro
For over 20 years, Smartsheet has empowered teams to manage work seamlessly and scale solutions smarter. Now, in our most ambitious chapter yet, we are uniting human teams with AI agents. By orchestrating the work agents do best, automating manual tasks and uncovering insights at scale, we create the space for people to focus on what truly matters: judgment, creativity, and big thinking. That is magic at work, and it’s what we show up for every day.Developer Community Manager Location: Bengaluru, India
Sep 01, 2026
Full time
For over 20 years, Smartsheet has empowered teams to manage work seamlessly and scale solutions smarter. Now, in our most ambitious chapter yet, we are uniting human teams with AI agents. By orchestrating the work agents do best, automating manual tasks and uncovering insights at scale, we create the space for people to focus on what truly matters: judgment, creativity, and big thinking. That is magic at work, and it’s what we show up for every day.Developer Community Manager Location: Bengaluru, India
Role Description We are seeking an Associate Software Engineer to support the design, development, testing, deployment, and maintenance of secure and user-friendly software applications. Working under the guidance of senior engineers, this role will contribute to front-end development, back-end API integration, software testing, defect resolution, and production support. The engineer will collaborate with product managers, UX/UI designers, developers, QA professionals, and DevOps teams to deliver reliable and scalable software solutions. The role also includes quality assurance responsibilities such as test planning, test execution, defect management, regression testing, and test automation to ensure applications meet functional, performance, accessibility, and usability requirements before release. Roles and Responsibilities Software Development Contribute to the design, development, testing, deployment, and maintenance of software applications. Work with senior engineers to implement features based on business, technical, and user-experience requirements. Develop front-end applications using React, Vite, TypeScript or JavaScript, HTML5, and CSS3. Build reusable, responsive, and accessible user-interface components following enterprise design standards. Collaborate with UX/UI designers to translate wireframes, prototypes, and mockups into functional interfaces. Integrate front-end applications with RESTful APIs and back-end services. Contribute to back-end API development using Python and FastAPI under the guidance of senior engineers. Support integration with enterprise applications, databases, identity platforms, cloud services, and third-party APIs. Participate in software design discussions, peer code reviews, and technical walkthroughs. Follow coding standards, secure development practices, and reusable software-design patterns. Develop and maintain unit, integration, and end-to-end automated tests. Troubleshoot and resolve software defects, integration issues, and performance problems. Support CI/CD processes for automated build, testing, security scanning, and deployment. Create and maintain technical documentation, including API details, configuration instructions, deployment steps, and support procedures. Support application monitoring, production issue investigation, and operational improvements. Participate in Agile ceremonies, including sprint planning, backlog refinement, daily stand-ups, demonstrations, and retrospectives. Stay current with emerging software-development, cloud, testing, security, and AI technologies. Quality Assurance Participate in test planning, test-case design, and test execution for new features and enhancements. Develop, execute, and maintain functional, integration, regression, smoke, user-interface, and end-to-end test cases. Perform manual testing and contribute to automated testing using appropriate frameworks. Validate application functionality, usability, accessibility, data accuracy, and API behavior. Identify, document, prioritize, and track software defects using tools such as Jira or Azure DevOps. Validate defect fixes and perform regression testing to ensure application stability. Collaborate with developers, product owners, and UX/UI designers to ensure requirements are testable and acceptance criteria are clear. Support User Acceptance Testing by preparing test data, validating functionality, documenting results, and assisting business users. Contribute to release-readiness reviews and confirm that software meets established quality standards before production deployment. Support continuous improvement of testing processes, automation coverage, defect prevention, and overall software quality. Security and Quality Follow secure software-development practices, including input validation, secure API usage, authentication, authorization, and secrets handling. Support the remediation of findings from application-security and code-quality tools such as Veracode, SonarQube, Snyk, Checkmarx, or equivalent platforms. Assist with dependency scanning, static code analysis, container scanning, and security validation within CI/CD pipelines. Follow OWASP guidance and enterprise security standards when developing and testing applications. Basic Qualifications and Experience Bachelor’s degree with 2–6 years of experience in Computer Science, Information Technology, Software Engineering, Engineering, or a related field. Functional Skills Must-Have Skills Understanding of information systems, software-development principles, and the software-development lifecycle. Hands-on experience with HTML5, CSS3, JavaScript or TypeScript. Familiarity with React and Vite, Angular, Vue.js, or another modern front-end framework. Understanding of component-based architecture, responsive design, application state, routing, and reusable UI development. Familiarity with web accessibility standards and practices, including WCAG. Ability to work with RESTful APIs and integrate front-end applications with back-end systems. Basic knowledge of Python and FastAPI or a comparable back-end framework. Understanding of relational databases, SQL, and basic data-access concepts. Experience developing, testing, debugging, and deploying software applications. Understanding of software-testing methodologies, including functional, integration, regression, smoke, end-to-end, and user acceptance testing. Experience creating and executing test cases and documenting test results. Basic experience with unit and UI testing frameworks such as Jest, React Testing Library, Cypress, Playwright, Selenium, or equivalent tools. Understanding of REST API testing using Postman or an equivalent tool. Familiarity with defect lifecycle management using Jira, Azure DevOps, or a similar platform. Familiarity with Git-based version control, branching, pull requests, and code reviews. Understanding of Agile and Scrum delivery methodologies. Basic understanding of CI/CD pipelines and automated software deployment. Understanding of secure coding principles, OWASP guidance, authentication, authorization, and dependency security. Strong analytical, debugging, troubleshooting, and problem-solving skills. Good-to-Have Skills Experience with React, Vite, TypeScript, and modern front-end development tools. Familiarity with FastAPI, including request validation, API endpoints, authentication, error handling, and automated testing. Familiarity with AWS, Azure, or Google Cloud, with AWS preferred. Exposure to AWS services such as S3, Lambda, API Gateway, ECS, RDS, DynamoDB, or CloudWatch. Basic experience with Docker and containerized application development. Familiarity with Infrastructure as Code, DevOps, and cloud-native development concepts. Familiarity with UI component libraries and design systems such as Material UI, Ant Design, or Fluent UI. Exposure to monitoring and logging tools such as CloudWatch, Grafana, Splunk, Datadog, or equivalent platforms. Familiarity with application-security and code-quality tools such as Veracode, SonarQube, Snyk, or equivalent platforms. Understanding of data validation, data quality, privacy, and governance concepts. Exposure to AI/ML-enabled applications or Generative AI technologies such as Large Language Models, Retrieval-Augmented Generation, and AI-assisted development tools. Familiarity with GitHub Copilot, OpenAI Codex, Cursor, or equivalent enterprise-approved development tools. Experience working within biotechnology, pharmaceutical, life sciences, manufacturing, or another regulated industry. Soft Skills Strong analytical and troubleshooting abilities. Effective verbal and written communication skills. Ability to collaborate effectively with technical and non-technical team members. Eagerness to learn and adapt to new technologies and development practices. Ability to manage multiple tasks with appropriate guidance and minimal supervision. Team-oriented mindset with a commitment to shared goals. Strong sense of ownership, accountability, and attention to detail. Ability to receive feedback, apply coaching, and continuously improve. Commitment to software quality, security, accessibility, and user experience.
Sep 01, 2026
Full time
Role Description We are seeking an Associate Software Engineer to support the design, development, testing, deployment, and maintenance of secure and user-friendly software applications. Working under the guidance of senior engineers, this role will contribute to front-end development, back-end API integration, software testing, defect resolution, and production support. The engineer will collaborate with product managers, UX/UI designers, developers, QA professionals, and DevOps teams to deliver reliable and scalable software solutions. The role also includes quality assurance responsibilities such as test planning, test execution, defect management, regression testing, and test automation to ensure applications meet functional, performance, accessibility, and usability requirements before release. Roles and Responsibilities Software Development Contribute to the design, development, testing, deployment, and maintenance of software applications. Work with senior engineers to implement features based on business, technical, and user-experience requirements. Develop front-end applications using React, Vite, TypeScript or JavaScript, HTML5, and CSS3. Build reusable, responsive, and accessible user-interface components following enterprise design standards. Collaborate with UX/UI designers to translate wireframes, prototypes, and mockups into functional interfaces. Integrate front-end applications with RESTful APIs and back-end services. Contribute to back-end API development using Python and FastAPI under the guidance of senior engineers. Support integration with enterprise applications, databases, identity platforms, cloud services, and third-party APIs. Participate in software design discussions, peer code reviews, and technical walkthroughs. Follow coding standards, secure development practices, and reusable software-design patterns. Develop and maintain unit, integration, and end-to-end automated tests. Troubleshoot and resolve software defects, integration issues, and performance problems. Support CI/CD processes for automated build, testing, security scanning, and deployment. Create and maintain technical documentation, including API details, configuration instructions, deployment steps, and support procedures. Support application monitoring, production issue investigation, and operational improvements. Participate in Agile ceremonies, including sprint planning, backlog refinement, daily stand-ups, demonstrations, and retrospectives. Stay current with emerging software-development, cloud, testing, security, and AI technologies. Quality Assurance Participate in test planning, test-case design, and test execution for new features and enhancements. Develop, execute, and maintain functional, integration, regression, smoke, user-interface, and end-to-end test cases. Perform manual testing and contribute to automated testing using appropriate frameworks. Validate application functionality, usability, accessibility, data accuracy, and API behavior. Identify, document, prioritize, and track software defects using tools such as Jira or Azure DevOps. Validate defect fixes and perform regression testing to ensure application stability. Collaborate with developers, product owners, and UX/UI designers to ensure requirements are testable and acceptance criteria are clear. Support User Acceptance Testing by preparing test data, validating functionality, documenting results, and assisting business users. Contribute to release-readiness reviews and confirm that software meets established quality standards before production deployment. Support continuous improvement of testing processes, automation coverage, defect prevention, and overall software quality. Security and Quality Follow secure software-development practices, including input validation, secure API usage, authentication, authorization, and secrets handling. Support the remediation of findings from application-security and code-quality tools such as Veracode, SonarQube, Snyk, Checkmarx, or equivalent platforms. Assist with dependency scanning, static code analysis, container scanning, and security validation within CI/CD pipelines. Follow OWASP guidance and enterprise security standards when developing and testing applications. Basic Qualifications and Experience Bachelor’s degree with 2–6 years of experience in Computer Science, Information Technology, Software Engineering, Engineering, or a related field. Functional Skills Must-Have Skills Understanding of information systems, software-development principles, and the software-development lifecycle. Hands-on experience with HTML5, CSS3, JavaScript or TypeScript. Familiarity with React and Vite, Angular, Vue.js, or another modern front-end framework. Understanding of component-based architecture, responsive design, application state, routing, and reusable UI development. Familiarity with web accessibility standards and practices, including WCAG. Ability to work with RESTful APIs and integrate front-end applications with back-end systems. Basic knowledge of Python and FastAPI or a comparable back-end framework. Understanding of relational databases, SQL, and basic data-access concepts. Experience developing, testing, debugging, and deploying software applications. Understanding of software-testing methodologies, including functional, integration, regression, smoke, end-to-end, and user acceptance testing. Experience creating and executing test cases and documenting test results. Basic experience with unit and UI testing frameworks such as Jest, React Testing Library, Cypress, Playwright, Selenium, or equivalent tools. Understanding of REST API testing using Postman or an equivalent tool. Familiarity with defect lifecycle management using Jira, Azure DevOps, or a similar platform. Familiarity with Git-based version control, branching, pull requests, and code reviews. Understanding of Agile and Scrum delivery methodologies. Basic understanding of CI/CD pipelines and automated software deployment. Understanding of secure coding principles, OWASP guidance, authentication, authorization, and dependency security. Strong analytical, debugging, troubleshooting, and problem-solving skills. Good-to-Have Skills Experience with React, Vite, TypeScript, and modern front-end development tools. Familiarity with FastAPI, including request validation, API endpoints, authentication, error handling, and automated testing. Familiarity with AWS, Azure, or Google Cloud, with AWS preferred. Exposure to AWS services such as S3, Lambda, API Gateway, ECS, RDS, DynamoDB, or CloudWatch. Basic experience with Docker and containerized application development. Familiarity with Infrastructure as Code, DevOps, and cloud-native development concepts. Familiarity with UI component libraries and design systems such as Material UI, Ant Design, or Fluent UI. Exposure to monitoring and logging tools such as CloudWatch, Grafana, Splunk, Datadog, or equivalent platforms. Familiarity with application-security and code-quality tools such as Veracode, SonarQube, Snyk, or equivalent platforms. Understanding of data validation, data quality, privacy, and governance concepts. Exposure to AI/ML-enabled applications or Generative AI technologies such as Large Language Models, Retrieval-Augmented Generation, and AI-assisted development tools. Familiarity with GitHub Copilot, OpenAI Codex, Cursor, or equivalent enterprise-approved development tools. Experience working within biotechnology, pharmaceutical, life sciences, manufacturing, or another regulated industry. Soft Skills Strong analytical and troubleshooting abilities. Effective verbal and written communication skills. Ability to collaborate effectively with technical and non-technical team members. Eagerness to learn and adapt to new technologies and development practices. Ability to manage multiple tasks with appropriate guidance and minimal supervision. Team-oriented mindset with a commitment to shared goals. Strong sense of ownership, accountability, and attention to detail. Ability to receive feedback, apply coaching, and continuously improve. Commitment to software quality, security, accessibility, and user experience.
Company Description It all started when engineer Fred Luddy wrote code that automated a tedious task for his coworker, Phyllis. She cried tears of joy. That moment inspired Fred to build a company that could do that for everyone—freeing people from busywork so they could focus on meaningful work. Today, ServiceNow is the AI control tower for business reinvention. Our ServiceNow AI platform brings together any AI, any data, and any workflow— helping 85% of the Fortune 500® work smarter, faster, and better. We're building an AI-native culture where technology and talent are unstoppable together. And we're just getting started. Join us to put AI to work for people. Job Description About the team The CRM & Industry Workflows (CRM&I) engineering organisation builds the products at the heart of ServiceNow's CRM vision: Workplace Service Delivery (WSD), Customer Service Management, Field Service Management, Sales & Order Management, and the shared CRM Foundation that connects them. Our teams span IDC, AMS, and EMEA, and our work ranges from core platform integrations to the agentic experiences that define how enterprises serve their employees and customers at scale. Engineering here has fundamentally changed. AI is not a productivity add-on — it is the default operating model. We are rebuilding how products are specified, how code is generated and verified, and what individual engineering excellence looks like. If you want to be at the leading edge
Aug 31, 2026
Full time
Company Description It all started when engineer Fred Luddy wrote code that automated a tedious task for his coworker, Phyllis. She cried tears of joy. That moment inspired Fred to build a company that could do that for everyone—freeing people from busywork so they could focus on meaningful work. Today, ServiceNow is the AI control tower for business reinvention. Our ServiceNow AI platform brings together any AI, any data, and any workflow— helping 85% of the Fortune 500® work smarter, faster, and better. We're building an AI-native culture where technology and talent are unstoppable together. And we're just getting started. Join us to put AI to work for people. Job Description About the team The CRM & Industry Workflows (CRM&I) engineering organisation builds the products at the heart of ServiceNow's CRM vision: Workplace Service Delivery (WSD), Customer Service Management, Field Service Management, Sales & Order Management, and the shared CRM Foundation that connects them. Our teams span IDC, AMS, and EMEA, and our work ranges from core platform integrations to the agentic experiences that define how enterprises serve their employees and customers at scale. Engineering here has fundamentally changed. AI is not a productivity add-on — it is the default operating model. We are rebuilding how products are specified, how code is generated and verified, and what individual engineering excellence looks like. If you want to be at the leading edge
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
Aug 31, 2026
Full time
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
Aug 31, 2026
Full time
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
Aug 31, 2026
Full time
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
Aug 31, 2026
Full time
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
Aug 31, 2026
Full time
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
Aug 31, 2026
Full time
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
Aug 31, 2026
Full time
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
Aug 31, 2026
Full time
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
Aug 31, 2026
Full time
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
Aug 31, 2026
Full time
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
Aug 31, 2026
Full time
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
Aug 31, 2026
Full time
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical verification, debugging LVS mismatches at 2 a.m. and hunting down obscure DRC violations that block tapeout. The difference between a runset that works and one that causes three weeks of respins is something you understand viscerally, and you are the engineer who catches the edge case before it becomes a customer escalation. You are fluent in the language of foundries, process nodes, and design rules. When a new technology node drops, you do not wait for perfect documentation. You dig into the specs, write test cases, script your way through qualification, and deliver a working rule deck while others are still scheduling kickoff meetings. Perl, Tcl, and Python are not just tools for you, they are how you turn repetitive manual work into reliable automation. Mentorship matters to you. You have seen junior engineers struggle with the same problems you solved years ago, and you take the time to walk them through it, not just hand them the answer. When a customer calls with a complex layout issue, you can translate their panic into a structured debug plan and explain the root cause in a way that makes sense to both the designer and the FAE. At Synopsys, you will work on IC Validator runsets for the most advanced process nodes in the industry, directly with foundries and customers who depend on what you build. What You'll Be Doing Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market The Impact You Will Have Enable first-pass silicon success for customers by delivering robust, accurate PV runsets that catch real issues without false noise Accelerate IC Validator adoption at top foundries and design houses, directly contributing to Synopsys revenue and market share in the PV space Reduce customer tapeout delays by providing fast, expert resolution to verification blockers that would otherwise cost weeks of schedule slip Build automation that scales across multiple process nodes and customer engagements, multiplying your impact beyond individual projects Shape the future roadmap of IC Validator by feeding real-world customer pain points and competitive insights back to the product development team Strengthen foundry partnerships through technical excellence and responsiveness, making Synopsys the go-to EDA partner for next-generation process nodes Grow the technical capability of the team by sharing knowledge, creating reusable scripts, and documenting solutions that become team standards What You'll Need B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, you have written and debugged complex runsets in at least one of these tools Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield Experience working with foundry PDKs and translating process rules into executable verification decks, exposure to sub-10nm nodes is a strong plus Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms Who You Are You can take a 500-page foundry design manual and turn it into a working DRC deck without needing someone to hold your hand through every rule When an LVS run fails with 10,000 errors, you do not panic, you filter the noise, find the root cause, and fix it systematically You are comfortable on a call with a stressed customer two days before tapeout, walking them through a layout issue while keeping them confident the problem will get solved Mentoring is not a checkbox for you, when a junior engineer asks a question, you take the time to explain the why, not just the what You stay current on process technology and EDA tool developments because you are genuinely curious, not because it is in a performance goal You can manage three runset development projects, two customer escalations, and a foundry qualification cycle at the same time without dropping threads or missing deadlines The Team You'll Be Part Of You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #TPG
Group Purpose Integrated Signal Management group is responsible for the direction and strategy for safety signal detection and management, safety governance, and quality complaints trending and analytics. It drives policies, research, innovation, and implementation of best practices in safety data mining, statistical signal detection, signal management and tracking, product complaint trending and analytics, risk management, benefit-risk assessment, and safety communications. Job Summary The Senior Data Scientist applies advanced expertise in statistics, data science, and analytical methodologies to support pharmacovigilance, safety signal detection, post-marketing surveillance, and safety decision-making within Global Patient Safety. The role works closely with Therapeutic Area Safety, Integrated Signal Management, and cross-functional partners to design and execute complex analyses using internal safety data, spontaneous reporting systems, real-world data, and other safety-relevant data sources. This role applies and evaluates a range of analytical approaches including frequentist and Bayesian signal detection methods, temporal and trending analyses, observational data methods, and emerging machine learning and artificial intelligence techniques. The role is responsible for translating complex safety questions into appropriate analytical designs, developing reproducible and scalable analytical workflows, evaluating methodological assumptions and limitations, and communicating scientifically defensible findings to technical and non-technical stakeholders. Through the application of advanced analytics, automation, visualization, and innovative data science methods, the Senior Data Scientist helps strengthen Amgen's safety surveillance capabilities, improve analytical efficiency, and enable timely, data-driven decisions that support patient safety. Key Activities 1. Provides data science and statistical support for safety surveillance, signal detection, and signal assessment activities. 2. Partners with TA Safety and Integrated Signal Management to develop and execute analytical approaches for safety questions and post-marketing surveillance. 3. Applies frequentist, Bayesian, temporal, and other fit-for-purpose statistical methods used in pharmacovigilance. 4. Analyzes internal safety data, spontaneous reporting data, real-world data, and other relevant sources to generate actionable insights. 5. Develops reproducible analytical workflows using programming, automation, and visualization technologies. 6. Evaluates and applies advanced analytics, machine learning, NLP, and AI-enabled approaches to support safety surveillance and analytical efficiency. 7. Communicates analytical methods, findings, limitations, and recommendations clearly to cross-functional stakeholders. Knowledge and Skills Strong background in statistics and complex statistical analysis. Proficiency in one or more analytical programming languages such as Python, R, SQL, or SAS Working knowledge of machine learning and emerging AI methods Strong communication skills. Ability to lead/influence cross-functional teams. Ability to manage multiple projects and priorities simultaneously. Ability to operate effectively in a cross-functional, matrixed environment. Preferred Knowledge of pharmacovigilance principles, safety signal detection, signal management, and post-marketing surveillance. Familiarity with pharmacovigilance and safety data sources, including spontaneous reporting systems, safety databases, and real-world data sources. Knowledge of frequentist and Bayesian statistical approaches used in safety surveillance and signal detection Education (Basic) Doctorate degree and 2 years of Data Science / Statistics / Biostatistics / Epidemiology / Mathematics / or related quantitative experience; OR Master’s degree and 6 years of Data Science / Statistics / Biostatistics / Epidemiology / Mathematics / or related quantitative experience; OR Bachelor’s degree and 8 years of Data Science / Statistics / Biostatistics / Epidemiology / Mathematics / or related quantitative experience; OR Associate’s degree and 10 years of Data Science / Statistics / Biostatistics / Epidemiology / Mathematics / or related quantitative experience; Education & Experience (Preferred) 8-13 years of applied data science, statistics, analytics, or related quantitative experience Experience in pharmaceutical, biotechnology, pharmacovigilance, clinical safety, epidemiology, or another regulated healthcare environment Experience analyzing adverse event, spontaneous reporting, real-world, claims, EHR, or other healthcare data Experience with pharmacovigilance signal detection methodologies, including frequentist and/or Bayesian approaches Experience using Python OR SAS OR R and SQL or comparable analytical technologies hands with coding Experience with machine learning, NLP, or AI-enabled analytical methods is desirable Degree in Statistics, Biostatistics, Mathematics, Data Science, Epidemiology, Computer Science, Engineering, or another quantitative/scientific field
Aug 31, 2026
Full time
Group Purpose Integrated Signal Management group is responsible for the direction and strategy for safety signal detection and management, safety governance, and quality complaints trending and analytics. It drives policies, research, innovation, and implementation of best practices in safety data mining, statistical signal detection, signal management and tracking, product complaint trending and analytics, risk management, benefit-risk assessment, and safety communications. Job Summary The Senior Data Scientist applies advanced expertise in statistics, data science, and analytical methodologies to support pharmacovigilance, safety signal detection, post-marketing surveillance, and safety decision-making within Global Patient Safety. The role works closely with Therapeutic Area Safety, Integrated Signal Management, and cross-functional partners to design and execute complex analyses using internal safety data, spontaneous reporting systems, real-world data, and other safety-relevant data sources. This role applies and evaluates a range of analytical approaches including frequentist and Bayesian signal detection methods, temporal and trending analyses, observational data methods, and emerging machine learning and artificial intelligence techniques. The role is responsible for translating complex safety questions into appropriate analytical designs, developing reproducible and scalable analytical workflows, evaluating methodological assumptions and limitations, and communicating scientifically defensible findings to technical and non-technical stakeholders. Through the application of advanced analytics, automation, visualization, and innovative data science methods, the Senior Data Scientist helps strengthen Amgen's safety surveillance capabilities, improve analytical efficiency, and enable timely, data-driven decisions that support patient safety. Key Activities 1. Provides data science and statistical support for safety surveillance, signal detection, and signal assessment activities. 2. Partners with TA Safety and Integrated Signal Management to develop and execute analytical approaches for safety questions and post-marketing surveillance. 3. Applies frequentist, Bayesian, temporal, and other fit-for-purpose statistical methods used in pharmacovigilance. 4. Analyzes internal safety data, spontaneous reporting data, real-world data, and other relevant sources to generate actionable insights. 5. Develops reproducible analytical workflows using programming, automation, and visualization technologies. 6. Evaluates and applies advanced analytics, machine learning, NLP, and AI-enabled approaches to support safety surveillance and analytical efficiency. 7. Communicates analytical methods, findings, limitations, and recommendations clearly to cross-functional stakeholders. Knowledge and Skills Strong background in statistics and complex statistical analysis. Proficiency in one or more analytical programming languages such as Python, R, SQL, or SAS Working knowledge of machine learning and emerging AI methods Strong communication skills. Ability to lead/influence cross-functional teams. Ability to manage multiple projects and priorities simultaneously. Ability to operate effectively in a cross-functional, matrixed environment. Preferred Knowledge of pharmacovigilance principles, safety signal detection, signal management, and post-marketing surveillance. Familiarity with pharmacovigilance and safety data sources, including spontaneous reporting systems, safety databases, and real-world data sources. Knowledge of frequentist and Bayesian statistical approaches used in safety surveillance and signal detection Education (Basic) Doctorate degree and 2 years of Data Science / Statistics / Biostatistics / Epidemiology / Mathematics / or related quantitative experience; OR Master’s degree and 6 years of Data Science / Statistics / Biostatistics / Epidemiology / Mathematics / or related quantitative experience; OR Bachelor’s degree and 8 years of Data Science / Statistics / Biostatistics / Epidemiology / Mathematics / or related quantitative experience; OR Associate’s degree and 10 years of Data Science / Statistics / Biostatistics / Epidemiology / Mathematics / or related quantitative experience; Education & Experience (Preferred) 8-13 years of applied data science, statistics, analytics, or related quantitative experience Experience in pharmaceutical, biotechnology, pharmacovigilance, clinical safety, epidemiology, or another regulated healthcare environment Experience analyzing adverse event, spontaneous reporting, real-world, claims, EHR, or other healthcare data Experience with pharmacovigilance signal detection methodologies, including frequentist and/or Bayesian approaches Experience using Python OR SAS OR R and SQL or comparable analytical technologies hands with coding Experience with machine learning, NLP, or AI-enabled analytical methods is desirable Degree in Statistics, Biostatistics, Mathematics, Data Science, Epidemiology, Computer Science, Engineering, or another quantitative/scientific field
